1. Field of the Invention
The present invention relates to conductive vias of ceramic substrates. More particularly, the present invention relates to a suspension to fill blind vias or through vias in silicon with a conductive material that has a coefficient of thermal expansion closer to that of silicon, and the method of making the same.
2. Description of Related Art
Packaging of integrated circuits is required for electrical interconnection, and thermal management, as well as mechanical integrity of the IC. Numerous types of electronic packages are available. Two common forms of high-end packages are multilayer ceramic (MLC) substrates and multilayer organic substrates. These two packaging technologies are used for most high-end applications with each having particular advantages and disadvantages. The key advantages for ceramic packages include: 1) close thermal expansion matching of the substrate to the IC; 2) good thermal conduction to aid in heat dissipation from the IC; and 3) high level integration allowing for complex wiring schemes. Some common limitations of ceramic packages are associated with the inferior dielectric properties of the ceramic, such as higher k-values, relative to organic packaging materials, as well as larger feature sizes in the structure, due to limitations associated with thick film processing.
Organic packaging technology improves on some of the limitations associated with ceramic packaging technology. Organic packages are mainly produced using photopatterning processes, which are capable of producing much smaller wiring features compared to their ceramic counterparts. This allows for increased circuit densities and more compact designs. However, organic packages typically have lower thermal conductivity and a much higher coefficient of thermal expansion (CTE) when compared to ceramic substrates. These limitations may result in thermally induced stresses during processing. Consequently, the use of organic packages may lead to inferior reliability for the assembled module, which includes the IC and the substrate.
The thermal stresses are becoming increasingly important for the newer chip structures being developed and manufactured with low-k and ultra low-k dielectric materials. These materials have inferior mechanical properties to the historical oxide dielectrics used in previous generations of chips. Additionally, the newer packaging technologies require improved circuit densities, as well as improved thermal management.
Silicon would be an ideal candidate for complex electronic packaging. Since most integrated circuits are made with silicon, the thermal expansion of the chip would be essentially identical to that of the substrate, virtually eliminating thermally induced stresses between the chip and the substrate. Furthermore, processes are well established to produce high density, copper based, single or multi-level circuitry on silicon.
IC packages contain numerous wiring levels with circuits varying in scale from very fine to fairly large. The larger scale wiring levels are required for power distribution, as well as electrical interconnections from the chip package to the next level (second level) of interconnections, which is typically a circuit board or card. Feature sizes approach 100 to 1000 microns for second level interconnection. A processing issue associated with these large feature sizes in silicon is related to the formation of z-axis interconnections or vias. Formation of vias in silicon is typically performed using photo patterning, followed by some form of chemical etching, such as reactive ion etching (RIE). These processes generally form large diameter vias, either blind vias or through vias.
Metallization of vias is performed using vapor deposition, chemical vapor deposition (CVD) or physical vapor deposition (PVD), in addition to or in place of electrochemical plating. A major issue with these metallization schemes, especially for large diameter vias, is that the deposited via metallurgy induces very high stresses in the silicon in the immediate area surrounding the vias. These stresses are the result of the thermal expansion mismatch between the silicon and the via metallurgy. As the via diameter is increased, the thermal stresses associated with the metallized vias result in cracking of the silicon adjacent to the vias. Thus, the magnitude of the crack driving force (K) scales with the via diameter. These cracks can result in electrical or mechanical failure or both within the silicon package.
It remains a goal in the art to develop a method to fill blind vias or through vias in silicon with a conductive material that has a coefficient of thermal expansion closer to that of silicon. Moreover, those of skill in the art would prefer that the material exhibit excellent conductivity. It is also desired to completely fill the via with the conductive material since large gaps or voids at the silicon/conductive material interface may degrade the mechanical integrity of the device. Requirements for the vias generally include a resistance less than 0.3 ohms, low shrinkage for a gap-free fill, and a coefficient of thermal expansion very close to silicon.
In U.S. Pat. No. 5,337,475 issued to Aoude, et al., on Aug. 16, 1994, entitled “PROCESS FOR PRODUCING CERAMIC CIRCUIT STRUCTURES HAVING CONDUCTIVE VIAS,” an improved via-filling composition is taught for producing conductive vias in ceramic substrates having circuitry. The composition is a mixture of ceramic spheres and conductive metal particles. However, this art represents a glass ceramic co-fire application for composite vias. As such, green sheets are used as well as full paste compositions containing binders and the like. In the present invention co-firing the substrate is not performed since the vias being filled are in dense silicon. Moreover, the present invention does not require sintering to achieve a fully dense structure. Firing the present invention to full density is detrimental since it ultimately results in a large void formation due to the volumetric shrinkage that occurs during densification of the glass phase in the via. Last, the present invention discloses a paste free of binders to alleviate the problem of binder burnout.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a material and method to fill blind vias or through vias in silicon with a conductive material that has a coefficient of thermal expansion closer to that of silicon.
It is another object of the present invention to provide a material and method to completely fill a via with the conductive material capable of eliminating large gaps or voids at the silicon/conductive material interface.
It is yet another object of the present invention to provide a material to reduce the stresses resulting from the thermal expansion mismatch between silicon and via metallurgy.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.